The present invention relates to a technique for use in the manufacture of a semiconductor device; and, more particularly, the invention relates to a technique that is effective when applied to the manufacture of a semiconductor device which is equipped with a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a gate electrode obtained by stacking a polycrystalline silicon film and a tungsten silicide film one after another.
A gate electrode having a stacked structure consisting of a polycrystalline silicon film and a tungsten silicide film is formed by forming a gate insulating film over a semiconductor substrate, forming thereover a polycrystalline silicon film and a tungsten silicide film successively and then patterning this film stack.
Japanese Unexamined Patent Publication No. Hei 7(1995)-78991 describes a fabrication technique for use in the manufacture of a semiconductor device having a tungsten polycide film by stacking a tungsten silicide film over a polycrystalline silicon film, wherein the tungsten silicide film has a high silicon content portion in the vicinity of the interface with the polycrystalline silicon film, a low silicon content portion at the center and a high silicon content portion in the vicinity of the surface (refer to Patent Document 1).
Japanese Unexamined Patent Publication No. Hei 5(1993)-343352 describes a technique of forming a polycrystalline silicon film over a gate oxide film and depositing a WSix film thereover through a seed layer, such as a thin polycrystalline silicon film, whereby, owing to a natural oxide film on the surface of the polycrystalline silicon film buried inside, the interface with the WSix film becomes ideal, the WSix film has improved adhesion and a lowering of the resistance of the polycide can be attained (refer to Patent Document 2).
[Patent Document 1] Japanese Unexamined Patent Publication No. Hei 7(1995)-78991
[Patent Document 2] Japanese Unexamined Patent Publication No. Hei 5(1993)-343352